Designing a custom silicon chip is by no means easy, but design is not necessarily the hardest part of developing an ASIC (Application Specific Integrated Circuit). Proving that the system will work correctly when it comes out of the fab is by far the hardest step, and it’s the most critical for reducing development cost and timescales.

The Sapphyre technology from Cambridge Consultants is a development platform for creating custom DSP cores that can be used for silicon IP blocks and custom ASICs, and we are continually conscious of the need to minimise risk in ASIC development, and to get the chip right first time.

ASIC verification for processing cores has traditionally relied on three separate tools:

Software simulation – A model of what the processor instructions do on each cycle, used to develop source code and prove the processor architecture is fit for purpose. It is crucial that the results of the software simulator can be relied on, so we take care to make sure the software simulator for Sapphyre cores is cycle accurate.

Register Transfer Logic (RTL) simulation – This is a full, detailed simulation of the chip and is the backbone of any ASIC development. It’s used to prove the hardware design, and evaluate timing and power consumption. Unfortunately it can also be slow, taking hours to simulate seconds of real time operation.

Hardware emulation – This uses hardware to emulate the operation of some or all of the ASIC.

All three of these tools are extremely useful and powerful. The first two simulation mechanisms are used extensively by many ASIC developers, including us here Cambridge Consultants. However, they are slow compared to the ASIC being designed. RTL simulation can be so slow that running extensive testing of real user scenarios can often be impractical. Software simulators can be orders of magnitude faster, but are further abstracted from the ASIC design and are still very time-consuming when trying to get the level of test coverage needed to be confident in a silicon chip.

Hardware emulation on the other hand offers much faster performance and quicker testing. However creating an emulator can be time consuming, costly, and complicated. In fact emulator design can be so complicated that emulators often run at a small fraction of the intended clock rate or fundamentally differ from the ASIC at the design level, just to get them to run. These constraints obviously limit the usefulness of the resultant emulator. However the story for emulating Sapphyre cores is quite different.

As explained in an earlier blog in this series, Sapphyre cores have a large processing capacity but fundamentally clock at a relatively slow rate. This results in efficient low power cores but has a secondary advantage that the RTL design can be written to run well in both ASICs and Field Programmable Gate Arrays (FPGAs). As a result, we can use off the shelf FPGA boards, not just for emulating portions of a chip but to accurately emulate whole processing cores.

This provides us with an affordable, high speed, full system emulation; with real peripherals, real timing, and real IO interaction. Since this is running on commercial FPGA boards there is very little development overhead. Furthermore the flexibility of modern FPGA boards means that our emulation rigs are connected to a continuous integration system, allowing us to verify code and hardware design changes as they occur.

This realistic, high speed FPGA emulation allows us to perform evaluation of large software codebases for the ASIC in development during an overnight test, to prove that the ASIC is fit for purpose. This even allows Cambridge Consultants to develop the production software that is to run on the ASIC, to a high degree of accuracy, before the final chips are produced.

This level of emulation is all you could hope for to reduce the risk in ASIC development, but at Cambridge Consultants we go one step further. For some Sapphyre core designs, and using the latest FPGA technology, the Sapphyre cores can run real-time in an FPGA. Whilst they may not be the same size or power of an ASIC they can be used to create working prototypes. These FPGA Sapphyre solutions can become early entry products that can be used to prove a product’s appeal, and have a natural, low risk route to silicon. My colleague Tomoko will talk some more about that route to silicon in the next Sapphyre blog post – part 7.

Kalin Dimitrov