An Application Specific Integrated Circuit (ASIC) is, as its name suggests, an IC designed for a specific application and thus heavily optimised to its needs. It can achieve high performance and low power consumption at the same time, on a very small area of silicon. Also, an ASIC has much lower per-unit cost. All of these advantages can make it more desirable than a design with discrete, general purpose components.

ASICs are used for many applications, but sadly nothing comes for free and ASIC development has its own drawbacks and (substantial) costs. It is a common perception for those considering ASICs that such a development can take many years, cost tens of millions of dollars and is high risk. On top of such struggles the results are often inflexible, so for the subsequent product variant you’ll need to do the whole process again.

Over this series of blogs we have described a number of the advantages of the Sapphyre technology which Cambridge Consultants uses to develop custom digital signal processing cores for ASICs. As a result of these advances, Sapphyre offers a much more appealing route to ASIC.

For the conventional ASIC, highly optimised designs are complex and lead to long development times. However the Sapphyre techniques we’ve described make use of a library of proven execution units to quickly develop the initial structure before customisation. The Sapphyre platform includes a cycle accurate simulator that supports parallel development of software and ASIC hardware, which not only reduces time to tape-out but also means software and test environments are ready to go when the first chips come back. A Sapphyre ASIC development typically completes in under a year and our shortest record for a Sapphyre ASIC is just six months. Reducing the development timescales to this extent also results in much lower development costs.

A quickly finished job could be perceived as rushed, but the Sapphyre development process is not just fast but also low risk. We’ve described how Sapphyre ASICs can be rigorously tested on accurate, high speed emulators, before the design freeze. Much of this rigor comes from the fact that it is tested with real application software. This irons out any issues early, for both software and hardware. Furthermore, the Sapphyre includes hardware support for non-invasive debug, to track down bugs quickly in both the emulator and final ASIC.

Conventional ASICs achieve low power through fixed hardware pipeline designs. Such ASICs are not usually programmable and any bugs fixes, variants or improvements would require a re-spin. However Sapphyre cores contain a number of mechanisms to achieve low power whilst retaining programmability (such as built-in sleep operations and a low clock rate technique). Retaining programmability reduces the ASIC risk and allows the same chip to be used in a range of product variants.

Sapphyre cores can meet cost and power targets that are close to fixed ASIC designs, but for established products (once flexibility is no longer required) there is a further option for the application’s algorithms to be “frozen in silicon” by swapping the program memory to a compressed metal layer ROM. The associated reduction in power, silicon area and cost has made significant savings for clients whose Sapphyre solutions have sold high volumes.

However ASICs don’t only have advantages at high volumes and with Sapphyre having reduced the traditional barriers of development cost, timescales and inflexibility we find that clients create ASICs for other reasons. Some want to protect against obsolesce in parts. Some want to remove the cost of licensing IP. Some want to reduce the size or power of a product. In all cases the simpler, faster route to ASIC of the Sapphyre technology provides a solution to create a truly differentiating product.

This is the last blog in this Sapphyre series but if you would like more information about Sapphyre, visit the Cambridge Consultants website. Also watch out for the Cambridge Consultants’ Innovation Day event, taking place 15/16 November, which includes a demonstration of how Sapphyre can be used to create an ASIC for an application previously considered only possible using super computers.

Tomoko Hatori
Senior Engineer